initial importv0.9

5 files changed, 274 insertions, 0 deletions

diff --git a/fw_src/eepr_read.s b/fw_src/eepr_read.s
new file mode 100644
index 0000000..818208f
--- /dev/null
+++ b/fw_src/eepr_read.s
@@ -0,0 +1,32 @@
+
+RAM	equ	$0000
+EEPROM	equ	$b600
+
+REGBASE	equ	$1000
+BAUD	equ	$2b		; SCI Baud Rate Control
+SCCR2	equ	$2d		; SCI Control Register 2
+SCSR	equ	$2e		; SCI Status Register
+SCDR	equ	$2f		; SCI Data Register
+
+	org	RAM
+init:
+	lds	#$00ff			; init stack pointer
+	ldd	#$300c			; A=SCP1|SCP0, B=TE|RE
+	staa	REGBASE+BAUD		; 9600 bps
+	stab	REGBASE+SCCR2
+main:
+	ldx	#EEPROM
+loop1:
+	ldaa	0,X			; read byte
+	jsr	sci_txd			; acknowledge byte
+	inx
+	cpx	#EEPROM+512
+	bne	loop1
+end:
+	wai
+	bra	end
+sci_txd:
+	tst	REGBASE+SCSR
+	bpl	sci_txd			; wait until TDRE bit set
+	staa	REGBASE+SCDR
+	rts
diff --git a/fw_src/eepr_write.s b/fw_src/eepr_write.s
new file mode 100644
index 0000000..f2c0509
--- /dev/null
+++ b/fw_src/eepr_write.s
@@ -0,0 +1,100 @@
+
+RAM	equ	$0000
+EEPROM	equ	$b600
+EEPSIZE	equ	256
+
+REGBASE	equ	$1000
+BAUD	equ	$2b		; SCI Baud Rate Control
+SCCR2	equ	$2d		; SCI Control Register 2
+SCSR	equ	$2e		; SCI Status Register
+SCDR	equ	$2f		; SCI Data Register
+BPROT	equ	$35		; EEPROM block protect
+PPROG	equ	$3b
+
+	org	RAM
+init:
+	lds	#$00ff			; init stack pointer
+	ldd	#$330c			; A=SCP1|SCP0, B=TE|RE
+	staa	REGBASE+BAUD		; 1200 bps
+	stab	REGBASE+SCCR2
+main:
+	clr	REGBASE+BPROT
+	ldx	#EEPROM
+loop1:
+	bsr	sci_rxd			; receive byte
+	jsr     eepr_write		; write accu A to address X
+	bsr	sci_txd			; acknowledge byte
+	inx
+	cpx	#EEPROM+EEPSIZE
+	beq	done
+;	ldy	#$ffff
+loop2:
+;	dey
+;	beq     done			; timeout -> end of code
+;	jsr	sci_rx_tst		; byte received?
+;	beq     loop2
+	bra     loop1
+done:
+	ldaa	#$1f
+	staa	REGBASE+BPROT
+	jmp	EEPROM			; execute the program
+sci_rx_tst:
+	ldaa	REGBASE+SCSR
+	anda	#$20			; receive buf full?
+	rts				; return 0 if not
+sci_rxd:
+	ldaa	REGBASE+SCSR
+	bita	#%00001010		; OV or FE bits set ?
+	bne	init
+	anda	#%00100000		; RDRF bit set ?
+	beq	sci_rxd
+	ldaa	REGBASE+SCDR
+	rts
+sci_txd:
+	tst	REGBASE+SCSR
+	bpl	sci_txd			; wait until TDRE bit set
+	staa	REGBASE+SCDR
+	rts
+
+eepr_write:
+	tab
+	comb
+	orab	0,X
+	bne	_eepr_erase_ok
+	ldaa	#0e
+	rts
+	ldab	#%00010110		; BYTE=1, ERASE=1, EELAT=1
+;	stab	PPROG
+	stab	0,X
+	ldab	#%00010111		; BYTE=1, ERASE=1, EELAT=1, EEPGM=1
+;	stab	PPROG
+	bsr	delay10ms
+;	clr	PPROG
+_eepr_erase_ok:
+	cmpa	0,X
+	beq	_eepr_write_ok
+_xx0:
+	ldaa	#$01
+	rts
+
+	ldab	#%00000010		; EELAT=1
+	stab	REGBASE+PPROG
+	staa	0,X
+	ldab	#%00000011		; EELAT=1, EEPGM=1
+	stab	REGBASE+PPROG
+	bsr	delay10ms
+	clr	REGBASE+PPROG
+	ldaa	0,X			; read back for verifying
+	rts
+_eepr_write_ok:
+	ldaa	#0			; read back for verifying
+	rts
+
+delay10ms:				; 20000 cycles to eat at Eclk=2MHz
+	pshx
+	ldx	#3330			; 3330*6 = 19980 cycles
+_delay_10ms_l0:
+	dex
+	bne	_delay_10ms_l0
+	pulx
+	rts
diff --git a/fw_src/obsolete.c b/fw_src/obsolete.c
new file mode 100644
index 0000000..640f514
--- /dev/null
+++ b/fw_src/obsolete.c
@@ -0,0 +1,29 @@
+void dump_obj(struct obj *bo)
+{
+	int i;
+
+	for(i=0; i<(bo->end_addr-bo->start_addr); i++) {
+		printf("%02x ", bo->code[i]);
+		if((i+1)%16 == 0) printf("\n");
+	}
+	printf("\n");
+	return;
+}
+
+byte TalkPgm[256] = {
+0x8e,0x01,0xff,0xce,0x10,0x00,0x6f,0x2c,0xcc,0x30,0x0c,0xa7,0x2b,0xe7,0x2d,0x86,
+0x10,0x06,0x7e,0x00,0x12,0xb6,0x10,0x2e,0x84,0x20,0x27,0xf9,0xb6,0x10,0x2f,0x43,
+0x8d,0x46,0x2a,0x51,0x8d,0x33,0x8f,0x8d,0x30,0x17,0x8d,0x2d,0x8f,0x81,0xfe,0x26,
+0x0d,0xa6,0x00,0x8d,0x33,0x17,0x8d,0x21,0x16,0x08,0x5a,0x26,0xf4,0x3b,0x81,0xbe,
+0x26,0x16,0x17,0x8d,0x14,0xe7,0x00,0x18,0xce,0x00,0x01,0x18,0x09,0x26,0xfc,0xe6,
+0x00,0xf7,0x10,0x2f,0x08,0x4a,0x26,0xeb,0x3b,0xf6,0x10,0x2e,0xc5,0x0a,0x26,0xa0,
+0xc4,0x20,0x27,0xf5,0xf6,0x10,0x2f,0x39,0x18,0x8f,0xb6,0x10,0x2e,0x2a,0xfb,0x18,
+0x8f,0xb7,0x10,0x2f,0x39,0x81,0x7e,0x26,0x0c,0x30,0x8f,0x8d,0xeb,0x17,0x8d,0xe8,
+0x30,0xc6,0x09,0x20,0xac,0x81,0x3e,0x26,0x12,0x8d,0xce,0x17,0x8d,0xcb,0x8f,0x35,
+0x86,0x09,0x20,0xaf,0x86,0x4a,0x8d,0xd0,0x0f,0x20,0xfd,0x81,0x4a,0x26,0xb9,0x30,
+0xc6,0x09,0x3a,0x35,0xec,0x07,0x8d,0xc0,0x17,0x8d,0xbd,0xcc,0x00,0x98,0xed,0x07,
+0x20,0xc7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x7e,0x00,0x15,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,
+0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,
+0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,
+0x58,0x7e,0x00,0x58,0x7e,0x00,0x58,0x7e,0x00,0x00,0x7e,0x00,0x58,0x7e,0x00,0x58};
diff --git a/fw_src/talker.s b/fw_src/talker.s
new file mode 100644
index 0000000..0b9b612
--- /dev/null
+++ b/fw_src/talker.s
@@ -0,0 +1,100 @@
+
+******************************************************************************
+******************************************************************************
+
+BAUD	equ	$102b			; SCI Baud Rate Control
+SCCR2	equ	$102d			; SCI Control Register 2
+SCSR	equ	$102e			; SCI Status Register
+SCDR	equ	$102f			; SCI Data Register
+
+	org	$0000			; program start
+init:
+	lds	#$01ff			; init stack pointer
+	ldd	#$330c			; A=SCP1|SCP0, B=TE|RE
+	staa	BAUD			; => XX00 bps
+	stab	SCCR2
+	ldaa	#%10010000
+	tap
+idleloop:
+	bra	idleloop
+sci_srv:
+	bsr	sci_rxd
+	coma
+	bsr	sci_txd
+	bpl	hi_command
+	psha
+	bsr	sci_rxd
+	tab
+	pula
+	xgdx
+	bsr	sci_rxd
+	tab
+	bsr	sci_rxd
+	xgdx
+	cmpa	#$be
+	bne	read_mcu_mem
+write_mcu_mem:
+	bsr	sci_rxd
+	staa	0,X
+	inx
+	decb
+	bne	write_mcu_mem
+	rti
+hi_command:
+	cmpa	#$3e
+	beq	write_mcu_regs
+read_mcu_regs:
+	tsx				; SP -> X
+	xgdx				; X <-> D
+	bsr	sci_txd
+	tba
+	bsr	sci_txd
+	tsx
+	ldab	#9
+	bra	read_mcu_mem
+write_mcu_regs:
+	bsr	sci_rxd
+	tab
+	bsr	sci_rxd
+	xgdx
+;	txs
+	ldab	#9
+	bra	write_mcu_mem
+sci_rxd:
+	ldaa	SCSR
+	bita	#%00001010		; OV or FE bits set ?
+	bne	init
+	anda	#%00100000		; RDRF bit set ?
+	beq	sci_rxd
+	ldaa	SCDR
+	rts
+sci_txd:
+	tst	SCSR
+	bpl	sci_txd			; wait until TDRE bit set
+	staa	SCDR
+	rts
+swi_srv:
+	ldaa	#$4a
+	bsr	sci_txd
+	tsx
+	ldd	7,X
+	bsr	sci_txd
+	tba
+	bsr	sci_txd
+	ldd	#idleloop
+	std	7,X
+	ldab	#7
+read_mcu_mem:
+	ldaa	0,X
+	bsr	sci_txd
+	inx
+	decb
+	bne	read_mcu_mem
+	rti
+
+	org	$00f1
+	jmp	sci_srv			; /XIRQ			** NEEDED **
+	jmp	swi_srv			; SWI			** NEEDED **
+	jmp	init			; Illegal opcode	** NEEDED **
+	jmp	init			; COP-Fail
+	jmp	init			; Clock Monitor Fail
diff --git a/fw_src/test.s b/fw_src/test.s
new file mode 100644
index 0000000..524aebc
--- /dev/null
+++ b/fw_src/test.s
@@ -0,0 +1,13 @@
+	org	$0100
+blink:
+	ldx	#REGBASE
+	bclr	PORTA,X #%00010000	; clear bit 5 of port A -> LED off
+loop_1:
+	inx
+	bne	loop_1
+	ldx	#REGBASE
+	bset	PORTA,X #%00010000	; set bit 5 of port A -> LED on
+loop_2:
+	dex
+	bne	loop_2
+	bra	blink